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NXP Semiconductors /QN908XC /FSP /FIR_CFG_CH0

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Interpret as FIR_CFG_CH0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FIR_CH0_COEF_BASE0FIR_CH0_TAP_LEN 0 (FIR_BUF_CLR_ALL)FIR_BUF_CLR_ALL 0 (FIR_CH0_BUF_CLR)FIR_CH0_BUF_CLR

Description

FIR channel 0 configuration register

Fields

FIR_CH0_COEF_BASE

FIR channel 0 coefficient base address
FIR_CH0_TAP_LEN

FIR channel 0 tap length the register value equals to real tap length minus 1.
FIR_BUF_CLR_ALL

clear all FIR buffer
FIR_CH0_BUF_CLR

FIR channel 0 buffer clear

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data